The fabrication of Flash Memories or electrically erasable programmable read only memories (EEPROMs) utilizing metal oxide semiconductor technology is well known in the prior art. These EEPROMs employ memory cells utilizing floating gates which are generally formed from polysilicon and which are completely surrounded by an insulator. Electrical charge is transferred into and removed from the floating gate to control the threshold voltage of one or more MOS transistors in a memory cell. The floating gate is programmed when a charge is stored in the floating gate. The cell is in an unprogrammed or erase state, when the floating gate is discharged.
One problem with the single transistor Flash cell or single-transistor EEPROM cell is the over-erase problem. An over-erase condition occurs when, as a result of erase, the floating gate potential is sufficiently high so that during a read operation an unselected cell conducts current, thereby providing an erroneous reading. A solution to the over-erase problem is disclosed in U.S. Pat. No. 4,797,856, the contents of which are incorporated by reference. However, the cell structure disclosed in this patent does not provide a constant preset read current.
Similarly, a split gate Flash memory structure is known to be able to prevent leakage problems even after over-erase. However, the split gate Flash cell cannot deliver a constant read current because for an over-erased cell the channel conduction under the floating gate increases as compared to a cell without over-erase.
Accordingly, it is an object of the present invention to provide a Flash memory cell or an EEPROM memory cell which does not exhibit the over-erase problem and which also delivers a preset constant read current.